![]() ![]() ![]() I'm not very experienced with programming, but I know enough to at least get me this far. The testbench output looks like this right now, where the first two numbers are each number to be summed, followed by the sum and the carry bit at the end: 0 + 0 = 0 | 0 Here's my main file, RCA.v: module RCA(CIN,A,B,S,C) Īnd this is my current testbench file, tb_RCA.v: `timescale 1ns / 1ps Is this something that could be easily achievable? I've completed my assignment and I'd like to make the output look something like this, with one table for sum output and one table for carry output: Sum:
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